1. Field of the Invention
The embodiments of the invention generally relate to devices having cross-coupled latches that require a balanced state. The balanced state being defined by an equal probability of the latch resolving to a “1” or a “0” when the cross-coupled data nodes are initialized to the same voltage. More particularly, this invention relates to a method of compensating for process-induced Random Device Variation (RDV). In addition, this method can also be applied to other threshold sensitive circuitry that can be affected by RDV. Sense-amplifier circuitry that requires matching characteristics between commonly enabled sense-amplifiers can also be calibrated using this approach.
2. Description of the Related Art
As technology scales to sub-micron geometries, Random Device Variation (RDV) is becoming more prominent. That is, as individual devices, such as field effect transistors (FETs), continue to shrink in size (e.g., from approximately 130 nm to 65 nm and below), threshold voltage variations between transistors formed on the same wafer have increased, for example, due to variations in dopant concentrations. These variations can limit the performance and/or reliability of circuits that incorporate such transistors. This is especially evident in the design of circuits with sub-components requiring a balanced state. For example, semiconductor memory arrays, such as static random access memory arrays (SRAMs), incorporate memory cells with cross-coupled transistors that require a balanced state to effectively store data and sense-amplifiers (SA) with cross-coupled transistors that require a balanced state to effectively detect small voltage signals on largely capacitive array lines. Mismatches between the cross-coupled transistors (i.e., variations in threshold voltage, length, width, and other device parameters between the cross-coupled transistors) in both the individual memory cells and the sense-amplifiers can produce incorrect results. Thus, in order to improve reliability, designers of such memory arrays typically tune their sensing circuits conservatively, thereby trading off performance in order to maintain a large sensing margin for reliable operation.